<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Cyclops on Matthew Penney</title><link>https://matthewpenney.net/tags/cyclops/</link><description>Recent content in Cyclops on Matthew Penney</description><generator>Hugo</generator><language>en-gb</language><lastBuildDate>Sat, 09 May 2026 17:50:18 +0100</lastBuildDate><atom:link href="https://matthewpenney.net/tags/cyclops/index.xml" rel="self" type="application/rss+xml"/><item><title>Reverse Engineering my CPU's Cache Sizes</title><link>https://matthewpenney.net/posts/cache_size/</link><pubDate>Sat, 09 May 2026 17:50:18 +0100</pubDate><guid>https://matthewpenney.net/posts/cache_size/</guid><description>&lt;p&gt;In this investigation, I aim to estimate the sizes of my CPU&amp;rsquo;s L1D and LLC
caches.&lt;/p&gt;
&lt;h2 id="general-approach-and-hypothesis"&gt;General Approach and Hypothesis&lt;/h2&gt;
&lt;p&gt;The approach I took was to process arrays of varying length and measure median
cache miss rates for each array size.&lt;/p&gt;
&lt;p&gt;Once the array exceeds the capacity of the CPU&amp;rsquo;s cache, I expect the cache
misses to sharply increase since the array no longer fits entirely in the
cache, and some reads will need to go to RAM or the next-level cache.&lt;/p&gt;</description></item></channel></rss>